Makefiles

If you take a look any average makefile, you end up seeing something similar to

LDFLAGS = -static

SRCS = myprogram.c
OBJS = ${SRCS:.c=.o}

.c.o: ${SRCS}
    ${CC} ${CFLAGS} $<

myprogram: ${OBJS}
    ${CC} -$@ ${LDFLAGS} ${OBJS}

And practically all of these are GNU make /only/.

Say you got a project like the one above, you got a file called myprogram.c that you want to turn into myprogram.

$ echo 'all: myprogram' >makefile
$ make
cc     myprogram.c   -o myprogram

make understands that since you're asking for it to compile myprogram, myprogram.c is the source.

And you don't need to specify how make is supposed to compile every single file, the most common filetypes like C source files already have prebuilt rules, so if your makefile looks something like

myprogram: myprogram.c utils.c

make understands that it has to compile myprogram.c and utils.c and link the compiled output to myprogram.

and if you add something to the LDFLAGS variable, make understands that too, be it through arguments, or through the makefile.

$ make LDFLAGS=-static
cc   -static  myprogram.c utils.c   -o myprogram

So, to summarize; make knows best, stop being so specific.